1. Field of the Invention
This invention relates to bipolar memory cells employing merged transistor logic (MTL) wherein control signals are passed through diodes (preferably Schottky diodes) to the base of transistors and there are no power sources uniquely dedicated to an individual cell.
2. Prior Art
S. K. Wiedmann in "Monolithically Integrated Storage Cell", IBM Technical Disclosure Bulletin, Vol. 22, No. 8A, January 1980 has disclosed the structure and use of high density static memories with extremely low power dissipation using merged transistor logic/integrated injection logic (MTL/I.sup.2 L).
FIG. 1 depicts an equivalent circuit schematic of the basic Wiedmann et al cell 10 (including bit lines 12 and 14, and word lines 16 and 18, i.e., access lines). As FIG. 1 shows, Wiedmann succeeded in eliminating resistors from cell 10 and feeding cell 10 with power through the word lines. The absence of resistors in the basic cell affords high packing density since resistors require physically distinct regions from the active device regions of cell transistors T.sub.1 and T.sub.2.
Further, in order to keep the power dissipated by static cell 10 low, the standby current must be very low. For a given supply voltage, this implies a need for a very high resistance (i.e., at least megaohoms or possible 10.sup.9 ohms) to minimize the standby current, which in turn requires large chip areas due to limitations on the sheet resistance of materials.
Feeding power and current to the cells through the word lines allows two resistors (i.e., the resistances asssociated with current sources connected to the word lines but not shown) to serve the same function for an entire column of memory cells as the resistors (not shown) normally included in each memory cell. This allows reduction of the overall size of the semiconductor memory for a given supply voltage as compared to memories where each cell includes its own power supply, while keeping the power dissipated the same.
Wiedmann provides power to T.sub.1 and T.sub.2 by using currrent injecting transistors T.sub.3 and T.sub.4. Transistors T.sub.1 and T.sub.3 form a first half of cell 10 (marked by dashed line 20). Likewise transistors T.sub.2 and T.sub.4 form the second half of cell 10, both halves being identical.
Each pair of transistors (i.e., T.sub.1 and T.sub.3, and T.sub.2 and T.sub.4) are connected in MTL/I.sup.2 L configuration. This configuration is well known. T.sub.1 and T.sub.2 are connected with their collector and base regions in the familiar cross-coupled relationship to provide a bistable, regenerative circuit. That is, the base 22 of T.sub.1 is connected to the collector 24 of T.sub.2 and the base 26 of T.sub.2 is connected to the collector 28 of T.sub.1. Reading in cell 10 is accomplished by sensing differential currents in conductors 30 and 32.
However, for I.sup.2 L, T.sub.1 and T.sub.2 operate in the inverse mode (i.e., current flow is in the direction which affords low current gain as contrasted with the normal or forward mode where current flows in the direction which affords high current gain). Processing of I.sup.2 L transistor configurations is more limited than the processing of configurations where the resulting transistors operate in the forward current mode because of the restrictions on doping profiles for I.sup.2 L.
As is well known, the current gain .beta. (i.e., collector current divided by base current) of a semiconductor transistor operating in the inverse mode is on the order of 2 to 10. However, .beta. for a transistor operating with normal or forward current flow is on the order of 20 to 100, or ten times that of I.sup.2 L. Thus base current in normally operating semiconductor transistors can be an order of magnitude less than base currents in inverse operating semiconductor transistors in order to provide the same collector current. Also a .beta. in the range of 50 is generally desired to insure stable, reproducible current conditions in a memory cell. Packing density is limited in I.sup.2 L due to limitations on the base width of transistors T.sub.3 and T.sub.4.
To achieve high packing density, low standby current and low power dissipation, it is therefore highly desirable to provide a solid state memory cell having no resistors in the basic cell structure, which is fed with power through the bit lines and/or word lines and which employs transistors operating in the normal or forward current mode.